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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Brcmstb PCIe Host Controller
maintainers:
- Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
properties:
compatible:
items:
- enum:
- brcm,bcm2711-pcie # The Raspberry Pi 4
- brcm,bcm4908-pcie
- brcm,bcm7211-pcie # Broadcom STB version of RPi4
- brcm,bcm7278-pcie # Broadcom 7278 Arm
- brcm,bcm7216-pcie # Broadcom 7216 Arm
- brcm,bcm7445-pcie # Broadcom 7445 Arm
- brcm,bcm7425-pcie # Broadcom 7425 MIPs
- brcm,bcm7435-pcie # Broadcom 7435 MIPs
reg:
maxItems: 1
interrupts:
minItems: 1
items:
- description: PCIe host controller
- description: builtin MSI controller
interrupt-names:
minItems: 1
items:
- const: pcie
- const: msi
ranges:
minItems: 1
maxItems: 4
dma-ranges:
minItems: 1
maxItems: 6
clocks:
maxItems: 1
clock-names:
items:
- const: sw_pcie
msi-controller:
description: Identifies the node as an MSI controller.
msi-parent:
description: MSI controller the device is capable of using.
brcm,enable-ssc:
description: Indicates usage of spread-spectrum clocking.
type: boolean
aspm-no-l0s: true
brcm,clkreq-mode:
description: A string that determines the operating
clkreq mode of the PCIe RC HW with respect to controlling the refclk
signal. There are three different modes -- "safe", which drives the
refclk signal unconditionally and will work for all devices but does
not provide any power savings; "no-l1ss" -- which provides Clock
Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
power savings. If the downstream device connected to the RC is L1SS
capable AND the OS enables L1SS, all PCIe traffic may abruptly halt,
potentially hanging the system; "default" -- which provides L0s, L1,
and L1SS, but not compliant to provide Clock Power Management;
specifically, may not be able to meet the T_CLRon max timing of 400ns
as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI
Express Mini CEM 2.1 specification. This situation is atypical and
should happen only with older devices.
$ref: /schemas/types.yaml#/definitions/string
enum: [ safe, no-l1ss, default ]
brcm,scb-sizes:
description: u64 giving the 64bit PCIe memory
viewport size of a memory controller. There may be up to
three controllers, and each size must be a power of two
with a size greater or equal to the amount of memory the
controller supports. Note that each memory controller
may have two component regions -- base and extended -- so
this information cannot be deduced from the dma-ranges.
$ref: /schemas/types.yaml#/definitions/uint64-array
items:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- ranges
- dma-ranges
- "#interrupt-cells"
- interrupts
- interrupt-names
- interrupt-map-mask
- interrupt-map
- msi-controller
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
- if:
properties:
compatible:
contains:
const: brcm,bcm4908-pcie
then:
properties:
resets:
items:
- description: reset controller handling the PERST# signal
reset-names:
items:
- const: perst
required:
- resets
- reset-names
- if:
properties:
compatible:
contains:
const: brcm,bcm7216-pcie
then:
properties:
resets:
items:
- description: phandle pointing to the RESCAL reset controller
reset-names:
items:
- const: rescal
required:
- resets
- reset-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
scb {
#address-cells = <2>;
#size-cells = <1>;
pcie0: pcie@7d500000 {
compatible = "brcm,bcm2711-pcie";
reg = <0x0 0x7d500000 0x9310>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie0>;
msi-controller;
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
brcm,enable-ssc;
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
/* PCIe bridge, Root Port */
pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pciclass,0604";
device_type = "pci";
vpcie3v3-supply = <&vreg7>;
ranges;
/* PCIe endpoint */
pci-ep@0,0 {
assigned-addresses =
<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pci14e4,1688";
};
};
};
};
|
