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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM8450 TLMM block
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,sm8450-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
gpio-reserved-ranges:
minItems: 1
maxItems: 105
gpio-line-names:
maxItems: 210
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sm8450-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sm8450-tlmm-state"
additionalProperties: false
$defs:
qcom-sm8450-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
required:
- pins
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sm8450-tlmm";
reg = <0x0f100000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 211>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
uart-w-state {
rx-pins {
pins = "gpio26";
function = "qup7";
bias-pull-up;
};
tx-pins {
pins = "gpio27";
function = "qup7";
bias-disable;
};
};
};
...
|
