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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Universal Flash Storage (UFS) Controller
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Andy Gross <agross@kernel.org>
# Select only our matches, not all jedec,ufs-2.0
select:
properties:
compatible:
contains:
const: qcom,ufshc
required:
- compatible
properties:
compatible:
items:
- enum:
- qcom,msm8994-ufshc
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
- qcom,sa8775p-ufshc
- qcom,sc7280-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
- qcom,sm6115-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
- qcom,sm8550-ufshc
- qcom,sm8650-ufshc
- const: qcom,ufshc
- const: jedec,ufs-2.0
clocks:
minItems: 8
maxItems: 11
clock-names:
minItems: 8
maxItems: 11
dma-coherent: true
interconnects:
minItems: 2
maxItems: 2
interconnect-names:
items:
- const: ufs-ddr
- const: cpu-ufs
iommus:
minItems: 1
maxItems: 2
phys:
maxItems: 1
phy-names:
items:
- const: ufsphy
power-domains:
maxItems: 1
qcom,ice:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the Inline Crypto Engine node
reg:
minItems: 1
maxItems: 2
reg-names:
items:
- const: std
- const: ice
required-opps:
maxItems: 1
resets:
maxItems: 1
'#reset-cells':
const: 1
reset-names:
items:
- const: rst
reset-gpios:
maxItems: 1
description:
GPIO connected to the RESET pin of the UFS memory device.
required:
- compatible
- reg
allOf:
- $ref: ufs-common.yaml
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8998-ufshc
- qcom,sa8775p-ufshc
- qcom,sc7280-ufshc
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
- qcom,sm8550-ufshc
- qcom,sm8650-ufshc
then:
properties:
clocks:
minItems: 8
maxItems: 8
clock-names:
items:
- const: core_clk
- const: bus_aggr_clk
- const: iface_clk
- const: core_clk_unipro
- const: ref_clk
- const: tx_lane0_sync_clk
- const: rx_lane0_sync_clk
- const: rx_lane1_sync_clk
reg:
minItems: 1
maxItems: 1
reg-names:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
then:
properties:
clocks:
minItems: 9
maxItems: 9
clock-names:
items:
- const: core_clk
- const: bus_aggr_clk
- const: iface_clk
- const: core_clk_unipro
- const: ref_clk
- const: tx_lane0_sync_clk
- const: rx_lane0_sync_clk
- const: rx_lane1_sync_clk
- const: ice_core_clk
reg:
minItems: 2
maxItems: 2
reg-names:
minItems: 2
required:
- reg-names
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-ufshc
then:
properties:
clocks:
minItems: 11
maxItems: 11
clock-names:
items:
- const: core_clk_src
- const: core_clk
- const: bus_clk
- const: bus_aggr_clk
- const: iface_clk
- const: core_clk_unipro_src
- const: core_clk_unipro
- const: core_clk_ice
- const: ref_clk
- const: tx_lane0_sync_clk
- const: rx_lane0_sync_clk
reg:
minItems: 1
maxItems: 1
reg-names:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- qcom,sm6115-ufshc
then:
properties:
clocks:
minItems: 8
maxItems: 8
clock-names:
items:
- const: core_clk
- const: bus_aggr_clk
- const: iface_clk
- const: core_clk_unipro
- const: ref_clk
- const: tx_lane0_sync_clk
- const: rx_lane0_sync_clk
- const: ice_core_clk
reg:
minItems: 2
maxItems: 2
reg-names:
minItems: 2
required:
- reg-names
# TODO: define clock bindings for qcom,msm8994-ufshc
- if:
required:
- qcom,ice
then:
properties:
reg:
maxItems: 1
clocks:
minItems: 8
maxItems: 8
else:
properties:
reg:
minItems: 1
maxItems: 2
clocks:
minItems: 8
maxItems: 11
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
ufs@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p5>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l9b_1p2>;
vccq-max-microamp = <1200000>;
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0xe0 0x0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz = <75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>;
qcom,ice = <&ice>;
};
};
|
