1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
|
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's ExynosAutov920 SADK board device tree source
*
* Copyright (c) 2023 Samsung Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "exynosautov920.dtsi"
#include "exynos-pinctrl.h"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Samsung ExynosAutov920 SADK board";
compatible = "samsung,exynosautov920-sadk", "samsung,exynosautov920";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &serial_0;
};
chosen {
stdout-path = &serial_0;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_wakeup &key_back>;
key-wakeup {
label = "KEY_WAKEUP";
linux,code = <KEY_WAKEUP>;
gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
wakeup-source;
};
key-back {
label = "KEY_BACK";
linux,code = <KEY_BACK>;
gpios = <&gpp6 3 GPIO_ACTIVE_LOW>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x70000000>,
<0x8 0x80000000 0x1 0xfba00000>,
<0xa 0x00000000 0x2 0x00000000>;
};
};
&pinctrl_alive {
key_wakeup: key-wakeup-pins {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
};
};
&pinctrl_peric1 {
key_back: key-back-pins {
samsung,pins = "gpp6-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_tout0>;
status = "okay";
};
&serial_0 {
status = "okay";
};
&usi_0 {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
};
&xtcxo {
clock-frequency = <38400000>;
};
|