dts/upstream/src/arm64/intel/socfpga_agilex_n6000.dts


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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2021-2022, Intel Corporation
 */
#include "socfpga_agilex.dtsi"

/ {
	model = "SoCFPGA Agilex n6000";
	compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";

	aliases {
		serial0 = &uart1;
		serial1 = &uart0;
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0x80000000 0 0>;
	};

	soc@0 {
		bus@80000000 {
			compatible = "simple-bus";
			reg = <0x80000000 0x60000000>,
				<0xf9000000 0x00100000>;
			reg-names = "axi_h2f", "axi_h2f_lw";
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;

			dma-controller@0 {
				compatible = "intel,hps-copy-engine";
				reg = <0x00000000 0x00000000 0x00001000>;
				#dma-cells = <1>;
			};
		};
	};
};

&osc1 {
	clock-frequency = <25000000>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&watchdog0 {
	status = "okay";
};

&fpga_mgr {
	status = "disabled";
};