aboutsummaryrefslogtreecommitdiff
path: root/dts/upstream/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi
blob: d1a7143ef3d406f691c7e6a7f0a141a00c0cc988 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP810 OCTA cores.
 */

#include "armada-ap810-ap0.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "marvell,armada-ap810-octa";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			enable-method = "psci";
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			enable-method = "psci";
		};
		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x100>;
			enable-method = "psci";
		};
		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x101>;
			enable-method = "psci";
		};
		cpu4: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x200>;
			enable-method = "psci";
		};
		cpu5: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x201>;
			enable-method = "psci";
		};
		cpu6: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x300>;
			enable-method = "psci";
		};
		cpu7: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x301>;
			enable-method = "psci";
		};
	};
};