aboutsummaryrefslogtreecommitdiff
path: root/dts/upstream/src/arm64/renesas/cat875.dtsi
blob: 8c9da8b4bd60bf325ebcd02e70904701e0f97428 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
 *
 * Copyright (C) 2019 Renesas Electronics Corp.
 */

/ {
	model = "Silicon Linux sub board for CAT874 (CAT875)";

	aliases {
		ethernet0 = &avb;
	};
};

&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";
	renesas,no-ether-link;
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id001c.c915",
			     "ethernet-phy-ieee802.3-c22";
		reg = <0>;
		interrupt-parent = <&gpio2>;
		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
	};
};

&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&pciec0 {
	status = "okay";
};

&pfc {
	avb_pins: avb {
		mux {
			groups = "avb_mii";
			function = "avb";
		};
	};

	can0_pins: can0 {
		groups = "can0_data";
		function = "can0";
	};

	can1_pins: can1 {
		groups = "can1_data";
		function = "can1";
	};
};