blob: ed88b4184413f26be8b9c835e9d262419dc5e3ea (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*/
/*
* P4080 DS board configuration file
* Also supports P4040 DS
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_PCIE3
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
|
