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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* include/configs/condor.h
* This file is Condor board configuration.
*
* Copyright (C) 2019 Renesas Electronics Corporation
*/
#ifndef __CONDOR_H
#define __CONDOR_H
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_BITBANGMII_MULTI
/* Environment compatibility */
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#endif /* __CONDOR_H */
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