blob: 246aa9b7ab99d25eb1c19c06a0a598b0e540cd77 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Samsung Electronics
*
* Common configuration settings for the SAMSUNG EXYNOS boards.
*/
#ifndef __EXYNOS_COMMON_H
#define __EXYNOS_COMMON_H
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
#include <linux/stringify.h>
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
/* select serial console configuration */
/* Miscellaneous configurable options */
#endif /* __CONFIG_H */
|
