blob: fcf1b7f990e19cd65539fb093c543a03631bb8fa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016, Imagination Technologies Ltd.
*
* Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
*
* Imagination Technologies Ltd. MIPSfpga
*/
#ifndef __XILFPGA_CONFIG_H
#define __XILFPGA_CONFIG_H
/* BootROM + MIG is pretty smart. DDR and Cache initialized */
#define CONFIG_SKIP_LOWLEVEL_INIT
/*--------------------------------------------
* CPU configuration
*/
/* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
/*----------------------------------------------------------------------
* Memory Layout
*/
/* SDRAM Configuration (for final code, data, stack, heap) */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */
/*----------------------------------------------------------------------
* Commands
*/
/*------------------------------------------------------------
* Console Configuration
*/
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* -------------------------------------------------
* Environment
*/
/* ---------------------------------------------------------------------
* Board boot configuration
*/
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#endif /* __XILFPGA_CONFIG_H */
|
