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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#ifndef __IMX8MM_EVK_H
#define __IMX8MM_EVK_H
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x920000
#define CONFIG_SPL_BSS_START_ADDR 0x910000
#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#endif
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
"fdt_addr_r=0x43000000\0" \
"boot_fit=no\0" \
"fdtfile=imx8mm-evk.dtb\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
#define IMX_FEC_BASE 0x30BE0000
#endif
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