blob: 2fb4764f7ce5984f924dc30acb7740c2aae10f8f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the SAMA5D4EK board.
*
* Copyright (C) 2014 Atmel
* Bo Shen <voice.shen@atmel.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "at91-sama5_common.h"
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x218000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif
|
