blob: 7dae56b236099c47eb73028a4b8f244bcb49591f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2019 Xilinx, Inc,
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/
#ifndef _VERSALPL_H_
#define _VERSALPL_H_
#include <xilinx.h>
#define VERSAL_PM_LOAD_PDI 0x701
#define VERSAL_PM_PDI_TYPE 0xF
extern struct xilinx_fpga_op versal_op;
#endif /* _VERSALPL_H_ */
|
