Merge git://git.denx.de/u-boot-x86

6 files changed, 47 insertions, 1 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 78532f56ca8..3fc3c5739ab 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -112,6 +112,7 @@ config X86
 	imply CMD_GETTIME
 	imply CMD_IO
 	imply CMD_IRQ
+	imply CMD_PCI
 	imply CMD_SF_TEST
 	imply CMD_ZBOOT
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c26710b484c..277c3babf37 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -401,6 +401,15 @@ config FSP_BROKEN_HOB
 	  do not overwrite the important boot service data which is used by
 	  FSP, otherwise the subsequent call to fsp_notify() will fail.
 
+config FSP_LOCKDOWN_SPI
+	bool
+	depends on HAVE_FSP
+	help
+	  Some Intel FSP (like Braswell) does SPI lock-down during the call
+	  to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
+	  for such FSP and U-Boot will configure the SPI opcode registers
+	  before the lock-down.
+
 config ENABLE_MRC_CACHE
 	bool "Enable MRC cache"
 	depends on !EFI && !SYS_COREBOOT
@@ -520,6 +529,13 @@ config AP_STACK_SIZE
 	  the memory used by this initialisation process. Typically 4KB is
 	  enough space.
 
+config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+	bool
+	help
+	  This option indicates that the turbo mode setting is not package
+	  scoped. i.e. turbo_enable() needs to be called on not just the
+	  bootstrap processor (BSP).
+
 config HAVE_VGA_BIOS
 	bool "Add a VGA BIOS image"
 	help
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
index 75dbbc27f12..1d876b19275 100644
--- a/arch/x86/cpu/baytrail/Kconfig
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -8,6 +8,7 @@ config INTEL_BAYTRAIL
 	bool
 	select HAVE_FSP if !EFI
 	select ARCH_MISC_INIT if !EFI
+	select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 	imply HAVE_INTEL_ME if !EFI
 	imply ENABLE_MRC_CACHE
 	imply AHCI_PCI
diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig
index 86a334047c0..2469b1e7c7a 100644
--- a/arch/x86/cpu/tangier/Kconfig
+++ b/arch/x86/cpu/tangier/Kconfig
@@ -16,6 +16,8 @@ config INTEL_TANGIER
 	imply USB
 	imply USB_DWC3
 
+if INTEL_TANGIER
+
 config SYS_CAR_ADDR
 	hex
 	default 0x19200000
@@ -30,3 +32,5 @@ config SYS_CAR_SIZE
 config SYS_USB_OTG_BASE
 	hex
 	default 0xf9100000
+
+endif
diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c
index bbd255efc0a..c0bff75c4f1 100644
--- a/arch/x86/cpu/turbo.c
+++ b/arch/x86/cpu/turbo.c
@@ -14,7 +14,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+#ifdef CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 static inline int get_global_turbo_state(void)
 {
 	return TURBO_UNKNOWN;
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 3397bb83eaf..1714d13228e 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -19,6 +19,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern void ich_spi_config_opcode(struct udevice *dev);
+
 int checkcpu(void)
 {
 	return 0;
@@ -49,6 +51,28 @@ void board_final_cleanup(void)
 {
 	u32 status;
 
+#ifdef CONFIG_FSP_LOCKDOWN_SPI
+	struct udevice *dev;
+
+	/*
+	 * Some Intel FSP (like Braswell) does SPI lock-down during the call
+	 * to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
+	 * it's bootloader's responsibility to configure the SPI controller's
+	 * opcode registers properly otherwise SPI controller driver doesn't
+	 * know how to communicate with the SPI flash device.
+	 *
+	 * Note we cannot do such configuration elsewhere (eg: during the SPI
+	 * controller driver's probe() routine), because:
+	 *
+	 * 1). U-Boot SPI controller driver does not set the lock-down bit
+	 * 2). Any SPI transfer will corrupt the contents of these registers
+	 *
+	 * Hence we have to do it right here before SPI lock-down bit is set.
+	 */
+	if (!uclass_first_device_err(UCLASS_SPI, &dev))
+		ich_spi_config_opcode(dev);
+#endif
+
 	/* call into FspNotify */
 	debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
 	status = fsp_notify(NULL, INIT_PHASE_BOOT);