Merge tag 'fsl-qoriq-2023-7-6' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next

Enable DM Serial for ls1043ardb and ls1046ardb/afrwy
Fixed secure boot on LS-CH2 platforms

13 files changed, 125 insertions, 20 deletions

diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index e75226bc434..5a8c382ed75 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -45,7 +45,7 @@ config ESBC_HDR_LS
 
 config ESBC_ADDR_64BIT
 	def_bool y
-	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
+	depends on FSL_LAYERSCAPE
 	help
 	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
 
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 884bdad196b..5e02cd91d75 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -7,7 +7,7 @@
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
 
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
 
 / {
 	model = "LS1043A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi
new file mode 100644
index 00000000000..ef31c79fa06
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+#include "fsl-ls1043a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 9e7c79fd2b9..f5b3bb68b3d 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -9,13 +9,17 @@
  */
 
 /dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
 
 / {
 	model = "LS1043A RDB Board";
 
         aliases {
 		spi1 = &dspi0;
+		serial0 = &duart0;
+		serial1 = &duart1;
+		serial2 = &duart2;
+		serial3 = &duart3;
         };
 
 };
diff --git a/arch/arm/dts/fsl-ls1043a-u-boot.dtsi b/arch/arm/dts/fsl-ls1043a-u-boot.dtsi
new file mode 100644
index 00000000000..65a870511c1
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&duart0 {
+	bootph-all;
+};
+
+&duart1 {
+	bootph-all;
+};
+
+&duart2 {
+	bootph-all;
+};
+
+&duart3 {
+	bootph-all;
+};
+
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 4960973a603..21643a1d951 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -8,7 +8,9 @@
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
 
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
 	compatible = "fsl,ls1043a";
@@ -223,28 +225,32 @@
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0500 0x0 0x100>;
 			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		duart1: serial@21c0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0600 0x0 0x100>;
 			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		duart2: serial@21d0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0500 0x0 0x100>;
 			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		duart3: serial@21d0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0600 0x0 0x100>;
 			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(1)>;
 		};
 
 		lpuart0: serial@2950000 {
diff --git a/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi
new file mode 100644
index 00000000000..ce204e675b3
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+#include "fsl-ls1046a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts
index 1e656d49602..ba10d212f1a 100644
--- a/arch/arm/dts/fsl-ls1046a-frwy.dts
+++ b/arch/arm/dts/fsl-ls1046a-frwy.dts
@@ -7,17 +7,37 @@
  */
 
 /dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
 
 / {
 	model = "LS1046A FRWY Board";
 
 	aliases {
 		spi0 = &qspi;
+		serial0 = &duart0;
+		serial1 = &duart1;
+		serial2 = &duart2;
+		serial3 = &duart3;
 	};
 
 };
 
+&duart0 {
+	status = "okay";
+};
+
+&duart1 {
+	status = "okay";
+};
+
+&duart2 {
+	status = "okay";
+};
+
+&duart3 {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index fec5c8ddb23..d66824975c5 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -7,7 +7,7 @@
  * Mingkai Hu <Mingkai.hu@nxp.com>
  */
 
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
 
 / {
 	model = "LS1046A QDS Board";
diff --git a/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi
new file mode 100644
index 00000000000..ce204e675b3
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+#include "fsl-ls1046a-u-boot.dtsi"
+
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 464129291c9..66d718905c7 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -9,17 +9,29 @@
  */
 
 /dts-v1/;
-/include/ "fsl-ls1046a.dtsi"
+#include "fsl-ls1046a.dtsi"
 
 / {
 	model = "LS1046A RDB Board";
 
 	aliases {
 		spi0 = &qspi;
+		serial0 = &duart0;
+		serial1 = &duart1;
+		serial2 = &duart2;
+		serial3 = &duart3;
 	};
 
 };
 
+&duart0 {
+	status = "okay";
+};
+
+&duart1 {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 
diff --git a/arch/arm/dts/fsl-ls1046a-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-u-boot.dtsi
new file mode 100644
index 00000000000..65a870511c1
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&duart0 {
+	bootph-all;
+};
+
+&duart1 {
+	bootph-all;
+};
+
+&duart2 {
+	bootph-all;
+};
+
+&duart3 {
+	bootph-all;
+};
+
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 060dc399c2f..44ee4c5808d 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -8,7 +8,9 @@
  * Mingkai Hu <mingkai.hu@nxp.com>
  */
 
-/include/ "skeleton64.dtsi"
+#include "skeleton64.dtsi"
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
 	compatible = "fsl,ls1046a";
@@ -222,29 +224,37 @@
 		duart0: serial@21c0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0500 0x0 0x100>;
-			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		duart1: serial@21c0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x00 0x21c0600 0x0 0x100>;
-			interrupts = <0 54 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		duart2: serial@21d0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0500 0x0 0x100>;
-			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		duart3: serial@21d0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21d0600 0x0 0x100>;
-			interrupts = <0 55 0x4>;
-			clocks = <&clockgen 4 0>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(2)>;
+			status = "disabled";
 		};
 
 		lpuart0: serial@2950000 {