diff options
| author | Vivek Gautam | 2013-09-14 14:02:50 +0530 |
|---|---|---|
| committer | Marek Vasut | 2013-10-20 23:42:38 +0200 |
| commit | a6c86decbb27e3d1e64af222d3179a88d0ea0a0d (patch) | |
| tree | 1ef03a87e789e152b25f46504edeb1d68600f5dd /include | |
| parent | 28cfef5f41b8d35a447ac99e747622e5d47ae04c (diff) | |
config: arm: exynos5250: Define CONFIG_SYS_CACHELINE_SIZE
XHCI stack driver needs this to align buffers to
CacheLine boundary. So define the same to be '64'
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/exynos5250-dt.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 8c21909d634..c9c19a75f33 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -37,6 +37,8 @@ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA #define CONFIG_SHA_HW_ACCEL |