diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/psci-common.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci.c | 12 |
3 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 52f18565db2..c4bbcc3cc3e 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -75,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - DSB; + dsb(); } /* Invalidate TLB */ @@ -88,9 +88,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* Full system ISB - make sure the instruction stream sees it */ - ISB; + isb(); } void invalidate_dcache_all(void) @@ -194,10 +194,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* ISB - make sure the instruction stream sees it */ - ISB; + isb(); } #else void invalidate_icache_all(void) diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c index d14b6937473..8cb4107be61 100644 --- a/arch/arm/cpu/armv7/psci-common.c +++ b/arch/arm/cpu/armv7/psci-common.c @@ -29,7 +29,7 @@ static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; void __secure psci_save_target_pc(int cpu, u32 pc) { psci_target_pc[cpu] = pc; - DSB; + dsb(); } u32 __secure psci_get_target_pc(int cpu) diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 7ac84065f4a..766b8c79d93 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms) u32 reg = ONE_MS * ms; cp15_write_cntp_tval(reg); - ISB; + isb(); cp15_write_cntp_ctl(3); do { - ISB; + isb(); reg = cp15_read_cntp_ctl(); } while (!(reg & BIT(2))); cp15_write_cntp_ctl(0); - ISB; + isb(); } static void __secure clamp_release(u32 __maybe_unused *clamp) @@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void) static void __secure cp15_write_scr(u32 scr) { asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr)); - ISB; + isb(); } /* @@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void) /* End of interrupt */ writel(reg, GICC_BASE + GICC_EOIR); - DSB; + dsb(); /* Get CPU number */ cpu = (reg >> 10) & 0x7; @@ -242,7 +242,7 @@ void __secure psci_cpu_off(void) /* Ask CPU0 via SGI15 to pull the rug... */ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); - DSB; + dsb(); /* Wait to be turned off */ while (1) |