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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi11
-rw-r--r--arch/arm/dts/imx8qm-dmsse20-a1.dts397
-rw-r--r--arch/arm/include/asm/arch-mx6/clock.h2
-rw-r--r--arch/arm/mach-imx/imx8/Kconfig8
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig7
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c36
-rw-r--r--arch/arm/mach-imx/mx6/clock.c66
-rw-r--r--arch/arm/mach-imx/romapi.c2
9 files changed, 495 insertions, 35 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8c10346a965..935b2f1517f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -961,6 +961,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
imx8qm-cgtqmx8.dtb \
+ imx8qm-dmsse20-a1.dtb \
imx8qm-rom7720-a1.dtb \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 00000000000..46a4dfe4e8a
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+};
+
+&uart1 { /* console */
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts
new file mode 100644
index 00000000000..cff150de07c
--- /dev/null
+++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x80000000 0x00020000;
+
+#include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
+
+/ {
+ model = "Advantech iMX8QM DMSSE20";
+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+ aliases {
+ mmc0 = &usdhc1;
+ mmc2 = &usdhc3;
+ };
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon";
+ stdout-path = &lpuart0;
+ };
+
+ reg_usb_otg1_vbus: usb_otg1_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx8qm-mek {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
+ >;
+ };
+
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
+ SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020
+ SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020
+ SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
+ SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
+ SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
+ SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
+ SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
+ SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
+ SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
+ SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
+ SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
+ SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
+ SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
+ SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
+ SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c
+ SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_DMA_UART0_RX 0x06000020
+ SC_P_UART0_TX_DMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_rtc_mc_8803: rtc-mc-8803-grp{
+ fsl,pins = <
+ SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c
+ SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020
+ SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc3_gpio: usdhc3grpgpio {
+ fsl,pins = <
+ SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
+ SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
+ SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
+ SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
+ SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
+ SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
+ SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
+ SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
+ SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
+ SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
+ SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
+ SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
+ SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
+ SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
+ SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
+ SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
+ SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
+ SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
+ SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
+ SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+ >;
+ };
+ };
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usdhc3 {
+ bus-width = <4>;
+ cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-names = "default","state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+ wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&fec1 {
+ fsl,ar8031-phy-fixup;
+ fsl,magic-packet;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+ };
+};
+
+&fec2 {
+ fsl,ar8031-phy-fixup;
+ fsl,magic-packet;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec2>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_mc_8803>;
+ status = "okay";
+
+ rv8803@32 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microcrystal,rv8803";
+ reg = <0x32>;
+ };
+
+ 24c02@50 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+};
+
+&lpuart0 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 8ae49715789..81af89c631f 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -41,6 +41,8 @@ enum mxc_clock {
MXC_SATA_CLK,
MXC_NFC_CLK,
MXC_I2C_CLK,
+ MXC_LCDIF1_CLK,
+ MXC_LCDIF2_CLK,
};
enum ldb_di_clock {
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 018b87b85b7..15f844f5030 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -91,6 +91,13 @@ config TARGET_IMX8QM_ROM7720_A1
select SUPPORT_SPL
select IMX8QM
+config TARGET_IMX8QM_DMSSE20_A1
+ bool "Support i.MX8QM DMS-SE20-A1 board"
+ select BINMAN
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select IMX8QM
+
config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BINMAN
@@ -105,6 +112,7 @@ endchoice
source "board/freescale/imx8qm_mek/Kconfig"
source "board/freescale/imx8qxp_mek/Kconfig"
source "board/congatec/cgtqmx8/Kconfig"
+source "board/advantech/imx8qm_dmsse20_a1/Kconfig"
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
source "board/toradex/apalis-imx8/Kconfig"
source "board/toradex/colibri-imx8x/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index dc51f971d45..7639439bdc9 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -60,6 +60,12 @@ config TARGET_IMX8MQ_PHANBELL
select IMX8MQ
select IMX8M_LPDDR4
+config TARGET_IMX8MQ_REFORM2
+ bool "imx8mq_reform2"
+ select BINMAN
+ select IMX8MQ
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
select BINMAN
@@ -362,6 +368,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/menlo/mx8menlo/Kconfig"
source "board/msc/sm2s_imx8mp/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/purism/librem5/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index df865e997d3..4705e6c1192 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -914,6 +914,8 @@ static int low_drive_gpu_freq(void *blob)
if (cnt != 7)
printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
+ if (cnt < 2)
+ return -1;
assignedclks[cnt - 1] = 200000000;
assignedclks[cnt - 2] = 200000000;
@@ -1395,40 +1397,6 @@ usb_modify_speed:
}
#endif
-#ifdef CONFIG_OF_BOARD_FIXUP
-#ifndef CONFIG_SPL_BUILD
-int board_fix_fdt(void *fdt)
-{
- if (is_imx8mpul()) {
- int i = 0;
- int nodeoff, ret;
- const char *status = "disabled";
- static const char * const dsi_nodes[] = {
- "/soc@0/bus@32c00000/mipi_dsi@32e60000",
- "/soc@0/bus@32c00000/lcd-controller@32e80000",
- "/dsi-host"
- };
-
- for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
- nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
- if (nodeoff > 0) {
-set_status:
- ret = fdt_setprop(fdt, nodeoff, "status", status,
- strlen(status) + 1);
- if (ret == -FDT_ERR_NOSPACE) {
- ret = fdt_increase_size(fdt, 512);
- if (!ret)
- goto set_status;
- }
- }
- }
- }
-
- return 0;
-}
-#endif
-#endif
-
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index cb9d629be40..1bdc568f9b1 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div, test_div, pll_num, pll_denom;
+ u64 temp64;
switch (pll) {
case PLL_SYS:
@@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
}
test_div = 1 << (2 - test_div);
- return infreq * (div + pll_num / pll_denom) / test_div;
+ temp64 = (u64)infreq;
+ temp64 *= pll_num;
+ do_div(temp64, pll_denom);
+ return infreq * div + (unsigned long)temp64;
default:
return 0;
}
@@ -414,6 +418,60 @@ static u32 get_uart_clk(void)
return freq / (uart_podf + 1);
}
+static u32 get_lcd_clk(unsigned int ifnum)
+{
+ u32 pll_rate;
+ u32 pred, postd;
+
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+ !is_mx6sll()) {
+ debug("This chip does't support lcd\n");
+ return 0;
+ }
+
+ pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK);
+ if (ifnum == 1) {
+ if (!is_mx6sl()) {
+ pred = __raw_readl(&imx_ccm->cscdr2);
+ pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK;
+ pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET;
+
+ postd = readl(&imx_ccm->cbcmr);
+ postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK;
+ postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+ } else {
+ pred = __raw_readl(&imx_ccm->cscdr2);
+ pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK;
+ pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET;
+
+ postd = readl(&imx_ccm->cscmr1);
+ postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET;
+ postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+ }
+ } else if (ifnum == 2) {
+ if (is_mx6sx()) {
+ pred = __raw_readl(&imx_ccm->cscdr2);
+ pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK;
+ pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET;
+
+ postd = readl(&imx_ccm->cscmr1);
+ postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK;
+ postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET;
+
+ } else {
+ goto if_err;
+ }
+ } else {
+ goto if_err;
+ }
+
+ return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1));
+
+if_err:
+ debug("This chip not support lcd iterface %d\n", ifnum);
+ return 0;
+}
+
static u32 get_cspi_clk(void)
{
u32 reg, cspi_podf;
@@ -744,6 +802,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
}
enable_lcdif_clock(base_addr, 1);
+ debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK));
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
@@ -765,6 +824,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
enable_lcdif_clock(base_addr, 1);
+ debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK));
}
}
@@ -1269,6 +1329,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_usdhc_clk(3);
case MXC_SATA_CLK:
return get_ahb_clk();
+ case MXC_LCDIF1_CLK:
+ return get_lcd_clk(1);
+ case MXC_LCDIF2_CLK:
+ return get_lcd_clk(2);
default:
printf("Unsupported MXC CLK: %d\n", clk);
break;
diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c
index b49e7f80a28..ff0522c2d11 100644
--- a/arch/arm/mach-imx/romapi.c
+++ b/arch/arm/mach-imx/romapi.c
@@ -70,6 +70,8 @@ enum boot_device get_boot_device(void)
boot_dev = SPI_NOR_BOOT;
break;
case BT_DEV_TYPE_USB:
+ if (!is_imx8ulp() && !is_imx9())
+ boot_instance = 0;
boot_dev = boot_instance + USB_BOOT;
break;
default:
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-20 16:40:38 +0000