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-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/dts/zynqmp-clk-ccf.dtsi4
-rw-r--r--arch/arm/dts/zynqmp.dtsi69
-rw-r--r--arch/microblaze/Kconfig2
-rw-r--r--arch/microblaze/cpu/exception.c2
-rw-r--r--arch/microblaze/cpu/spl.c12
-rw-r--r--arch/microblaze/cpu/start.S74
-rw-r--r--arch/microblaze/cpu/u-boot-spl.lds4
-rw-r--r--arch/microblaze/cpu/u-boot.lds2
-rw-r--r--arch/microblaze/include/asm/processor.h2
10 files changed, 101 insertions, 75 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 44954977b68..8fc18976896 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1207,7 +1207,7 @@ config ARCH_ZYNQMP
select DM_SERIAL
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
- select FIRMWARE
+ imply FIRMWARE
select GICV2
select GPIO_EXTRA_HEADER
select OF_CONTROL
@@ -1217,7 +1217,7 @@ config ARCH_ZYNQMP
select SPL_DM_SPI if SPI && SPL_DM
select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL
- select SPL_FIRMWARE if SPL
+ imply SPL_FIRMWARE if SPL
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
select ZYNQMP_IPI
@@ -1228,6 +1228,7 @@ config ARCH_ZYNQMP
imply FAT_WRITE
imply MP
imply DM_USB_GADGET
+ imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
config ARCH_TEGRA
bool "NVIDIA Tegra"
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index b27b0aaf7c9..664e65896d7 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -169,28 +169,24 @@
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
- clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gpio {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 1332f5373fb..755a4ed2e51 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -265,7 +265,7 @@
};
/* GDMA */
- fpd_dma_chan1: dma@fd500000 {
+ fpd_dma_chan1: dma-controller@fd500000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd500000 0x0 0x1000>;
@@ -276,9 +276,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14e8>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
- fpd_dma_chan2: dma@fd510000 {
+ fpd_dma_chan2: dma-controller@fd510000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd510000 0x0 0x1000>;
@@ -289,9 +290,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14e9>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
- fpd_dma_chan3: dma@fd520000 {
+ fpd_dma_chan3: dma-controller@fd520000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd520000 0x0 0x1000>;
@@ -302,9 +304,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ea>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
- fpd_dma_chan4: dma@fd530000 {
+ fpd_dma_chan4: dma-controller@fd530000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd530000 0x0 0x1000>;
@@ -315,9 +318,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14eb>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
- fpd_dma_chan5: dma@fd540000 {
+ fpd_dma_chan5: dma-controller@fd540000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd540000 0x0 0x1000>;
@@ -328,9 +332,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ec>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
- fpd_dma_chan6: dma@fd550000 {
+ fpd_dma_chan6: dma-controller@fd550000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd550000 0x0 0x1000>;
@@ -341,9 +346,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ed>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
- fpd_dma_chan7: dma@fd560000 {
+ fpd_dma_chan7: dma-controller@fd560000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd560000 0x0 0x1000>;
@@ -354,9 +360,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ee>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
- fpd_dma_chan8: dma@fd570000 {
+ fpd_dma_chan8: dma-controller@fd570000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xfd570000 0x0 0x1000>;
@@ -367,6 +374,7 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x14ef>;
power-domains = <&zynqmp_firmware PD_GDMA>;
+ #dma-cells = <1>;
};
gic: interrupt-controller@f9010000 {
@@ -396,7 +404,7 @@
* These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access.
*/
- lpd_dma_chan1: dma@ffa80000 {
+ lpd_dma_chan1: dma-controller@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa80000 0x0 0x1000>;
@@ -407,9 +415,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x868>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
- lpd_dma_chan2: dma@ffa90000 {
+ lpd_dma_chan2: dma-controller@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffa90000 0x0 0x1000>;
@@ -420,9 +429,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x869>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
- lpd_dma_chan3: dma@ffaa0000 {
+ lpd_dma_chan3: dma-controller@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaa0000 0x0 0x1000>;
@@ -433,9 +443,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86a>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
- lpd_dma_chan4: dma@ffab0000 {
+ lpd_dma_chan4: dma-controller@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffab0000 0x0 0x1000>;
@@ -446,9 +457,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86b>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
- lpd_dma_chan5: dma@ffac0000 {
+ lpd_dma_chan5: dma-controller@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffac0000 0x0 0x1000>;
@@ -459,9 +471,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86c>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
- lpd_dma_chan6: dma@ffad0000 {
+ lpd_dma_chan6: dma-controller@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffad0000 0x0 0x1000>;
@@ -472,9 +485,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86d>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
- lpd_dma_chan7: dma@ffae0000 {
+ lpd_dma_chan7: dma-controller@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffae0000 0x0 0x1000>;
@@ -485,9 +499,10 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86e>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
- lpd_dma_chan8: dma@ffaf0000 {
+ lpd_dma_chan8: dma-controller@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xffaf0000 0x0 0x1000>;
@@ -498,6 +513,7 @@
#stream-id-cells = <1>;
iommus = <&smmu 0x86f>;
power-domains = <&zynqmp_firmware PD_ADMA>;
+ #dma-cells = <1>;
};
mc: memory-controller@fd070000 {
@@ -527,12 +543,13 @@
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
- clock-names = "pclk", "hclk", "tx_clk";
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
};
gem1: ethernet@ff0c0000 {
@@ -541,12 +558,13 @@
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
- clock-names = "pclk", "hclk", "tx_clk";
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
};
gem2: ethernet@ff0d0000 {
@@ -555,12 +573,13 @@
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
- clock-names = "pclk", "hclk", "tx_clk";
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
};
gem3: ethernet@ff0e0000 {
@@ -569,12 +588,13 @@
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
- clock-names = "pclk", "hclk", "tx_clk";
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
};
gpio: gpio@ff0a0000 {
@@ -820,7 +840,7 @@
uart0: serial@ff000000 {
u-boot,dm-pre-reloc;
- compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
@@ -831,7 +851,7 @@
uart1: serial@ff010000 {
u-boot,dm-pre-reloc;
- compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
@@ -854,7 +874,7 @@
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
- dwc3_0: dwc3@fe200000 {
+ dwc3_0: usb@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
@@ -886,7 +906,7 @@
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
- dwc3_1: dwc3@fe300000 {
+ dwc3_1: usb@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
@@ -961,6 +981,7 @@
};
zynqmp_dpsub: display@fd4a0000 {
+ u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 99a17bccb38..a25a95a0131 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -15,6 +15,8 @@ config TARGET_MICROBLAZE_GENERIC
select DM_SERIAL
select OF_CONTROL
select SUPPORT_SPL
+ select SPL_LIBCOMMON_SUPPORT if SPL
+ select SPL_LIBGENERIC_SUPPORT if SPL
select SYSRESET
select DM_SPI
select DM_SPI_FLASH
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index b8dedc4e195..e9476abedbd 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -55,7 +55,7 @@ void _hw_exception_handler (void)
hang();
}
-#ifdef CONFIG_SYS_USR_EXCEP
+#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
void _exception_handler (void)
{
puts("User vector_exception\n");
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index 86522f84479..cea6d56f16f 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -12,12 +12,15 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/u-boot.h>
+#include <linux/stringify.h>
bool boot_linux;
-u32 spl_boot_device(void)
+void board_boot_order(u32 *spl_boot_list)
{
- return BOOT_DEVICE_NOR;
+ spl_boot_list[0] = BOOT_DEVICE_NOR;
+ spl_boot_list[1] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = BOOT_DEVICE_SPI;
}
/* Board initialization after bss clearance */
@@ -52,8 +55,9 @@ int spl_start_uboot(void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- __asm__ __volatile__ ("mts rmsr, r0;" \
- "bra r0");
+ __asm__ __volatile__ (
+ "mts rmsr, r0;" \
+ "brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR));
return 0;
}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 9479737aa29..645f7cb0389 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -15,7 +15,7 @@
_start:
mts rmsr, r0 /* disable cache */
- addi r8, r0, __end
+ addi r8, r0, _end
mts rslr, r8
#if defined(CONFIG_SPL_BUILD)
@@ -105,15 +105,17 @@ clear_bss:
* r10: Stores little/big endian offset for vectors
* r2: Stores imm opcode
* r3: Stores brai opcode
+ * r4: Stores the vector base address
*/
__setup_exceptions:
- addik r1, r1, -28
+ addik r1, r1, -32
swi r2, r1, 4
swi r3, r1, 8
- swi r6, r1, 12
- swi r7, r1, 16
- swi r8, r1, 20
- swi r10, r1, 24
+ swi r4, r1, 12
+ swi r6, r1, 16
+ swi r7, r1, 20
+ swi r8, r1, 24
+ swi r10, r1, 28
/* Find-out if u-boot is running on BIG/LITTLE endian platform
* There are some steps which is necessary to keep in mind:
@@ -125,33 +127,32 @@ __setup_exceptions:
* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
*/
addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
- lwi r7, r0, 0x28
- swi r6, r0, 0x28 /* used first unused MB vector */
- lbui r10, r0, 0x28 /* used first unused MB vector */
- swi r7, r0, 0x28
+ sw r6, r1, r0
+ lbu r10, r1, r0
/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
-#ifdef CONFIG_SYS_RESET_ADDRESS
+ /* Store the vector base address in r4 */
+ addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
+
/* reset address */
- swi r2, r0, 0x0 /* reset address - imm opcode */
- swi r3, r0, 0x4 /* reset address - brai opcode */
+ swi r2, r4, 0x0 /* reset address - imm opcode */
+ swi r3, r4, 0x4 /* reset address - brai opcode */
- addik r6, r0, CONFIG_SYS_RESET_ADDRESS
+ addik r6, r0, CONFIG_SYS_TEXT_BASE
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x2
- sh r7, r0, r8
+ sh r7, r4, r8
rsubi r8, r10, 0x6
- sh r6, r0, r8
-#endif
+ sh r6, r4, r8
-#ifdef CONFIG_SYS_USR_EXCEP
+#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
/* user_vector_exception */
- swi r2, r0, 0x8 /* user vector exception - imm opcode */
- swi r3, r0, 0xC /* user vector exception - brai opcode */
+ swi r2, r4, 0x8 /* user vector exception - imm opcode */
+ swi r3, r4, 0xC /* user vector exception - brai opcode */
addik r6, r5, _exception_handler
sw r6, r1, r0
@@ -177,42 +178,43 @@ __setup_exceptions:
*/
lhu r7, r1, r10
rsubi r8, r10, 0xa
- sh r7, r0, r8
+ sh r7, r4, r8
rsubi r8, r10, 0xe
- sh r6, r0, r8
+ sh r6, r4, r8
#endif
/* interrupt_handler */
- swi r2, r0, 0x10 /* interrupt - imm opcode */
- swi r3, r0, 0x14 /* interrupt - brai opcode */
+ swi r2, r4, 0x10 /* interrupt - imm opcode */
+ swi r3, r4, 0x14 /* interrupt - brai opcode */
addik r6, r5, _interrupt_handler
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x12
- sh r7, r0, r8
+ sh r7, r4, r8
rsubi r8, r10, 0x16
- sh r6, r0, r8
+ sh r6, r4, r8
/* hardware exception */
- swi r2, r0, 0x20 /* hardware exception - imm opcode */
- swi r3, r0, 0x24 /* hardware exception - brai opcode */
+ swi r2, r4, 0x20 /* hardware exception - imm opcode */
+ swi r3, r4, 0x24 /* hardware exception - brai opcode */
addik r6, r5, _hw_exception_handler
sw r6, r1, r0
lhu r7, r1, r10
rsubi r8, r10, 0x22
- sh r7, r0, r8
+ sh r7, r4, r8
rsubi r8, r10, 0x26
- sh r6, r0, r8
+ sh r6, r4, r8
- lwi r10, r1, 24
- lwi r8, r1, 20
- lwi r7, r1, 16
- lwi r6, r1, 12
+ lwi r10, r1, 28
+ lwi r8, r1, 24
+ lwi r7, r1, 20
+ lwi r6, r1, 16
+ lwi r4, r1, 12
lwi r3, r1, 8
lwi r2, r1, 4
- addik r1, r1, 28
+ addik r1, r1, 32
rtsd r15, 8
or r0, r0, r0
@@ -270,7 +272,7 @@ relocate_code:
add r23, r0, r7 /* Move reloc addr to r23 */
/* Relocate text and data - r12 temp value */
addi r21, r0, _start
- addi r22, r0, __end - 4 /* Include BSS too */
+ addi r22, r0, _end - 4 /* Include BSS too */
rsub r6, r21, r22
or r5, r0, r0
diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds
index 3387eb7189d..7883a64b158 100644
--- a/arch/microblaze/cpu/u-boot-spl.lds
+++ b/arch/microblaze/cpu/u-boot-spl.lds
@@ -53,10 +53,10 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
}
- __end = . ;
+ _end = . ;
}
#if defined(CONFIG_SPL_MAX_FOOTPRINT)
-ASSERT(__end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
+ASSERT(_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
"SPL image plus BSS too big");
#endif
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index 5dc09dbad2d..2b316cc7f5a 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -56,5 +56,5 @@ SECTIONS
. = ALIGN(4);
__bss_end = .;
}
- __end = . ;
+ _end = . ;
}
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index 16e0d0ef0a9..958018c1909 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -8,7 +8,7 @@
/* References to section boundaries */
-extern char __end[];
+extern char _end[];
extern char __text_start[];
/* Microblaze board initialization function */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-14 08:08:42 +0000