diff options
Diffstat (limited to 'board/keymile')
| -rw-r--r-- | board/keymile/secu1/qts/iocsr_config.h | 8 | ||||
| -rw-r--r-- | board/keymile/secu1/qts/pll_config.h | 136 | ||||
| -rw-r--r-- | board/keymile/secu1/qts/sdram_config.h | 140 |
3 files changed, 142 insertions, 142 deletions
diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h index 7640c56db16..9f05fce8b30 100644 --- a/board/keymile/secu1/qts/iocsr_config.h +++ b/board/keymile/secu1/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00100000, diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h index f0c31860ca4..7bc704a1820 100644 --- a/board/keymile/secu1/qts/pll_config.h +++ b/board/keymile/secu1/qts/pll_config.h @@ -6,78 +6,78 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 39 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 24 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 1 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 14 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 40000000 -#define CONFIG_HPS_CLK_OSC2_HZ 40000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 -#define CONFIG_HPS_CLK_USBCLK_HZ 12500000 -#define CONFIG_HPS_CLK_NAND_HZ 31250000 -#define CONFIG_HPS_CLK_SDMMC_HZ 3125000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 40000000 +#define CFG_HPS_CLK_OSC2_HZ 40000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 600000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 1953125 +#define CFG_HPS_CLK_USBCLK_HZ 12500000 +#define CFG_HPS_CLK_NAND_HZ 31250000 +#define CFG_HPS_CLK_SDMMC_HZ 3125000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h index b0ff86ef381..a0ce0b26ca9 100644 --- a/board/keymile/secu1/qts/sdram_config.h +++ b/board/keymile/secu1/qts/sdram_config.h @@ -8,76 +8,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x11 |