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path: root/arch/riscv/cpu/ax25
AgeCommit message (Expand)Author
2019-12-10riscv: ax25: cache: Add SPL_RISCV_MMODE for SPLRick Chen
2019-12-10riscv: ax25: add SPL supportRick Chen
2019-12-02common: Move ARM cache operations out of common.hSimon Glass
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass
2019-09-03riscv: cache: use CCTL to flush d-cacheRick Chen
2019-09-03riscv: cache: Flush L2 cache before jump to linuxRick Chen
2019-09-03riscv: ax25: add imply v5l2 cache controllerRick Chen
2019-08-26riscv: add run mode configuration for SPLLukas Auer
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner
2019-04-08riscv: ax25: Andes specific cache shall only support in M-modeRick Chen
2019-04-08riscv: ax25: Add platform-specific Kconfig optionsRick Chen
2019-01-15riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen
2018-10-03riscv: Move do_reset() to a common placeBin Meng
2018-10-03riscv: Make start.S available for all targetsBin Meng
2018-10-03riscv: Move the linker script to the CPU root directoryBin Meng
2018-08-20riscv: Include bss subsections in linker scriptAlexander Graf
2018-07-25efi_loader: Rename sections to allow for implicit dataAlexander Graf
2018-05-29riscv: cpu: nx25: Rename as ax25Rick Chen