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path: root/arch/riscv/cpu/cpu.c
AgeCommit message (Expand)Author
2023-02-01riscv: cpu: check U-Mode before counteren writeNikita Shubin
2022-11-15riscv: Fix detecting FPU support in standard extensionYu Chien Peter Lin
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen
2022-09-26spl: introduce SPL_XIP to configNikita Shubin
2022-03-10event: Convert arch_cpu_init_dm() to use eventsSimon Glass
2021-10-18riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas
2021-10-07sysreset: provide SBI based sysreset driverHeinrich Schuchardt
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek BehĂșn
2021-05-05riscv: cpu: Add callback to init each coreGreen Wan
2020-09-30riscv: Clear pending IPIs on initializationSean Anderson
2020-07-24riscv: Make SiFive HiFive Unleashed board boot againBin Meng
2020-07-01riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson
2020-07-01riscv: Clean up IPI initialization codeSean Anderson
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
2020-05-18common: Drop init.h from common headerSimon Glass
2019-08-26riscv: add run mode configuration for SPLLukas Auer
2019-08-15riscv: Access CSRs using CSR numbersBin Meng
2019-05-09riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen
2019-04-08riscv: add support for multi-hart systemsLukas Auer
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng
2018-12-18riscv: Probe cpus during bootBin Meng
2018-11-26riscv: save hart ID and device tree passed by prior boot stageLukas Auer
2018-10-03riscv: Add a helper routine to print CPU informationBin Meng