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AgeCommit message (Expand)Author
2023-04-20riscv: Support CONFIG_REMAKE_ELFSamuel Holland
2023-04-20riscv: Update alignment for some sections in linker scriptsBin Meng
2023-04-20riscv: spl: Remove relocation sectionsBin Meng
2023-04-20riscv: Avoid updating the link registerBin Meng
2023-04-20riscv: Change to use positive offset to access relocation entriesBin Meng
2023-04-20riscv: Optimize loading relocation typeBin Meng
2023-04-20riscv: Optimize source end address calculation in start.SBin Meng
2023-04-20riscv: Enforce DWARF4 outputBin Meng
2023-04-20riscv: Correct a comment in io.hBin Meng
2023-04-20riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device treeYanhong Wang
2023-04-20riscv: dts: jh7110: Add initial u-boot device treeYanhong Wang
2023-04-20riscv: dts: jh7110: Add initial StarFive JH7110 device treeYanhong Wang
2023-04-20board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigYanhong Wang
2023-04-20riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoCYanhong Wang
2023-04-20riscv: cpu: jh7110: Add support for jh7110 SoCYanhong Wang
2023-03-06riscv: semihosting: replace inline assembly with assembly fileAndre Przywara
2023-02-27Merge tag 'v2023.04-rc3' into nextTom Rini
2023-02-17riscv: binman: Add help message for missing blobsRick Chen
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang
2023-02-17configs: ae350: Enable v5l2 cache for AE350 platforms in SPLYu Chien Peter Lin
2023-02-17riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPLYu Chien Peter Lin
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin
2023-02-17riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()Yu Chien Peter Lin
2023-02-17riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang
2023-02-17riscv: global_data.h: Correct the comment for PLICSWYu Chien Peter Lin
2023-02-14dm: dts: Convert driver model tags to use new schemaSimon Glass
2023-02-10Correct SPL uses of LMBSimon Glass
2023-02-01riscv: memcpy: check src and dst before copyRick Chen
2023-02-01riscv: ax25: bypass malloc when spl fit boots from ramRick Chen
2023-02-01riscv: ae350: Enable CCTL_SUENRick Chen
2023-02-01riscv: cpu: check U-Mode before counteren writeNikita Shubin
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini
2023-01-09Merge branch 'next'Tom Rini
2022-12-29efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWAREHeinrich Schuchardt
2022-12-22Convert CONFIG_STANDALONE_LOAD_ADDR to KconfigTom Rini
2022-12-08arch/riscv: add semihosting support for RISC-VKautuk Consul
2022-11-15riscv: clarify meaning of CONFIG_SBI_V02Heinrich Schuchardt
2022-11-15riscv: Fix detecting FPU support in standard extensionYu Chien Peter Lin
2022-11-15riscv: dts: fix the mpfs's reference clock frequencyConor Dooley
2022-11-03riscv: dts: Add QSPI NAND device nodePadmarao Begari
2022-11-03riscv: dts: Update memory configurationPadmarao Begari
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass
2022-10-20riscv: andes_plic.c: use modified IPI schemeYu Chien Peter Lin
2022-10-20riscv: support building double-float modulesHeinrich Schuchardt
2022-10-07riscv: Fix build against binutils 2.38Alexandre Ghiti
2022-09-29dm: core: Drop ofnode_is_available()Simon Glass
2022-09-29treewide: Drop bootm_headers_t typedefSimon Glass
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ...Tom Rini
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen